1. Technical Field
The invention relates generally to integrated circuits, and more particularly, to an integrated circuit and method of forming same with increased electromigration lifetime and allowable current density using at least one vertically upwardly extending dummy via.
2. Background Art
Electromigration is a common cause of malfunction in interconnects of integrated circuits (ICs). Electromigration includes physical motion of atoms out of areas where current density is very high, which is caused primarily by frictional force between metal ions and flowing electrons. The eventual result is a break in a metal line, especially those made of aluminum (Al). This is the main reason why aluminum (Al) interconnects are being replaced with copper (Cu) interconnects in advanced IC technology. However, electromigration also occurs in copper (Cu) wiring due to copper diffusion during current flow. Much of the diffusion occurs at the interface between the top of the copper wiring and the dielectric cap, which is typically a thin layer of silicon nitride (Si3N4) or silicon carbide (SiC). Accordingly, one current challenge for advanced IC technologies is increasing electromigration lifetimes for back-end-of-line (BEOL) copper wiring or, in other words, increasing the allowable current densities in copper wiring.
There are a number of approaches to increase allowable current density for a given set of groundrules. In one approach, the cross-sectional wire area is increased by increasing wire height. This approach, however, results in an increase in capacitive coupling, and reduces the process window for damascene metal fill. Based on the knowledge that shorter run-lengths can have longer electromigration lifetimes, in another approach, long metal wire run-lengths are broken into shorter run-lengths by dropping them down to a lower wiring level or sending them up to an upper wiring level through a via to a short link at the lower or upper level. Then, the metal wiring is brought back to the original metal level through another via. The approach described, however, adds to the resistance of the wiring because the vias add significant resistance, and makes the circuit more prone to failure because of the various via failure modes. This approach is also expected to reduce circuit density because it requires wires to move up or down to other levels and then back, which expends density above and below.
Another approach to increase allowable current density is to use a selective metal cap deposition process to cap the metal lines before depositing the dielectric cap. This approach is disclosed in U.S. Pat. No. 6,342,733 B1 to Hu et al., which uses a metal cap such as cobalt-tungsten-phosphorous (CoWP). The approach described, however, adds cost and complexity. In addition, this approach raises concerns with shorting reliability failure due to spurious deposition between metal lines.
In a similar approach, the copper wiring is capped with refractory metal such as tantalum (Ta), tantalum nitride (TaN), etc., by using a “reverse liner” process. This process includes performing a slight etchback of the copper after chemical mechanical polishing (CMP), a blanket deposition of the refractory metal and CMP to remove the refractory metal in the field areas. While this approach enhances electromigration lifetimes, it also adds cost and complexity, and presents concerns with the process window across a wide range of pattern factors.
In another approach, metallic reservoirs in the form of passive or dummy vias are used on interconnects as a source or sink for electromigration material, slowing the build up of electromigration-induced mechanical stress. This approach is disclosed in U.S. Pat. No. 6,171,268 and related publications 2003/0067638 and 2003/0089996, all to Hau-Riege. This approach, however, does not slow metal diffusion, it merely provides a source of additional metal such that metal atoms diffusing out can be replaced, thus delaying the onset of a void in the metal. Similar approaches, which suffer from the same drawbacks, are disclosed in U.S. Pat. No. 6,489,684 to Chen et al. and JP 2000 012688A to Masaaki.
In view of the foregoing, there is a need in the art for a solution to increasing electromigration lifetimes of IC interconnects and increasing allowable current density that does not suffer from the problems of the related art.